The present invention relates to the manufacture of semiconductor integrated circuits and more particularly to a method of forming the STI oxide regions and alignment marks in a semiconductor structure provided with polysilicon filled deep trenches with only one masking step. STI (Shallow Trench Isolation) oxide regions are used to isolate devices from each other in the substrate and alignments marks are used in photolithography steps for reticle registration. The method finds extensive application in the field of DRAM (Dynamic Random Access Memory) and EDRAM (Embedded DRAM) chips where polysilicon filled deep and shallow trenches are formed in the semiconductor substrate.
In the manufacture of semiconductor integrated circuits and especially in DRAM/EDRAM chips having polysilicon filled deep and shallow trenches formed in a silicon substrate, a specific MUV photolithography mask is used to create the alignment marks in the silicon structure that are required for reticle registration during the subsequent photolithography steps. For instance, DRAM chips wherein the elementary storage cell is of the so-called xe2x80x9cBESTxe2x80x9d type are concerned by such a masking step. xe2x80x9cBESTxe2x80x9d cells are described in the IBM Journal of Research and Development, Vol. 39, No xc2xd January/March 1995, in an article entitled xe2x80x9cThe Evolution of IBM CMOS Technology by E. Adler et al, pp 167-185.
Basically, at the end of the Deep Trench (DT) module, capacitor deep trenches have been etched in the silicon substrate. Next, the so-called active areas (AAs) are formed using a first mask referred to as the AA mask. Active areas include the source/drain regions of all the Insulated Gate Field Effect Transistors (IGFETs). Then, shallow isolation trenches are formed and a layer of an oxide, referred to hereinbelow as the STI oxide, is deposited to conformally coat the wafer surface, in order to fill the shallow isolation trenches in excess. The STI oxide layer is then planarized, i.e. the oxide on top of the AAs is removed and the oxide in the shallow isolation trenches etched down to approximately the silicon substrate level to create the so-called STI oxide regions. The planarization step is generally performed by Chemical-Mechanical Planarization (CMP). At this stage of the fabrication process, the wafer surface is substantially planar. These steps which are carried out in the STI module aim to isolate AAs from each other by said STI oxide regions. Afterwards, well and surface implants are performed before the gate conductor (GC) stack is deposited. The delineation of the GC stack to define the IGFET gate conductors requires the deposition of a photoresist layer and a DUV mask. The implants require MUV masks to prevent some regions of the wafer from being implanted. In order to successfully register these masks (both MUV implant masks and DUV GC mask) with a good accuracy, it is necessary to create alignment marks at the wafer surface. To date, this is the role of an additional MUV mask, referred to as the KV mask, which is formed right after STI oxide region formation. The above conventional fabrication process to form the STI oxide regions and the alignment marks with two masking steps will be now described in more details in conjunction with FIGS. 1 and 2A-2I.
Turning to FIG. 1, there is shown the top view and a cross section taken along line aa thereof of a state-of-the-art semiconductor structure 10 which is part of the wafer at the end of the DT module, i.e. after polysilicon filled deep trenches have been formed. Basically, structure 10 consists of a silicon substrate 11 with a 140 nm thick Si3N4 pad layer 12 formed thereupon (the underlying SiO2 pad layer is not taken into consideration for the sake of simplicity). The Si3N4 pad layer is deposited on blanket wafers before deep trench formation, it will be used later on as an etch stop layer for various etch and CMP steps. As apparent in FIG. 1, two types of deep trenches labeled 13A and 13B have been formed in silicon substrate 11. Trenches 13A are formed in the xe2x80x9carrayxe2x80x9d areas where the elementary memory cells are fabricated. Each memory cell is comprised of an IGFET and its associated capacitor that is formed in a deep trench as standard. Trenches 13B are formed in the xe2x80x9csupportxe2x80x9d and in the xe2x80x9ckerfxe2x80x9d areas where one can find addressing circuits, drivers, . . . and measurement/alignment structures respectively. Some trenches 13B in the xe2x80x9ckerfxe2x80x9d areas will be used later on in the fabrication process as alignment marks. Deep trenches 13A and 13B are filled with polysilicon material as standard. The bottom part of the polysilicon fill 14xe2x80x2, referred to hereinbelow as POLY2 (POLY1 is not shown in FIG. 1), is isolated from the substrate by a collar oxide layer 15 and the top part 14xe2x80x3 is referred to hereinbelow as POLY3.
Now, the exposed polysilicon material of POLY3 is etched below substrate 11 surface to create recesses 16A and 16B that are shown in FIG. 2A. These recesses and this etch step will be referred to hereinbelow as RECESS3 and RECESS3 etch step respectively. Typically, the depth of RECESS3 in the silicon substrate 11 is about 50 nm. Note that the polysilicon of POLY3 is arsenic (As) doped so that the out diffusion of As atoms into the silicon substrate 11 will subsequently form a strap making an electrical connection between one electrode of the capacitor and the source/drain region of the IGFETs. The strap is xe2x80x9cburiedxe2x80x9d to avoid an electrical short between the capacitor and the passing word lines (WLs) that are the gate conductors of the IGFETs. The passing word lines will be defined later on in the wafer processing by the so-called GC mask of the DUV type.
A first masking step is now necessary to define the active areas (AAs). Turning to FIG. 2B, a 135 nm thick layer 17 of an anti-reflective coating (ARC) material is blanket deposited onto structure 10, followed by the deposition of a 625 nm thick layer 18 of a photoresist. Adequate materials are AR3 900 and M20G supplied by Shipley USA, Malborough, Mass., USA. The ARC material is not only used for its anti-reflective properties, but also as a planarizing medium. The photoresist layer 18 is baked, exposed, and developed as standard to leave a patterned layer, that will be referred to hereinbelow as the AA mask still bearing numeral 18.
After the AA mask 18 has been formed, the process continues with an adequate three-step anisotropic dry etch process, to remove the ARC, Si3N4, monocrystalline silicon of substrate 11, polysilicon of POLY3/POLY2 and the collar oxide in sequence with three different chemistries at locations that are not protected by the AA mask 18. This etch process is performed in the MxP chamber provided with an electrostatic chuck ESC S3 and a Vespel ring of an AME 5000, a tool sold by Applied Materials Inc, Santa Clara, Calif., USA.
Adequate operating conditions for each etch step are:
1. ARC Etching
2. Si3N4 Etching
3. Monocrystalline Silicon/POLY3/Collar Oxide Etching
This sequence of etching steps referred to hereinbelow as the AA/STI etch step is used to create the shallow isolation trenches and the active areas in the silicon substrate 11. Shallow isolation trenches will be subsequently filled with the STI oxide to form STI oxide regions. At this stage of the fabrication process, the structure 10 is shown in FIG. 2C. As apparent in FIG. 2C, the shallow isolation trenches referenced 19A are etched to a deepness below the silicon substrate 11 surface measured by parameter Dl which is equal to 260 nm in the instant case.
Residual ARC and photoresist materials of layers 17 and 18 are then removed from the wafer surface, using a conventional strip process exposing shallow isolation trenches 19A and recesses 16B as shown in FIG. 2D. At the end of that step, active areas are delineated as apparent in the top view of FIG. 2D where they are referenced 20.
Then, a layer 21 of oxide, referred to as the STI oxide, is conformally deposited onto the structure 10 by LPCVD as standard to fill shallow isolation trenches 19A and recesses 16B. Structure 10 is then planarized typically by chemical-mechanical polishing (CMP). The aim of this CMP planarization step is to remove the STI oxide in excess on top of the Si3N4 pad layer 12 and leave the STI oxide substantially filling the shallow isolation trenches 19A and recesses 16B forming STI oxide regions 21A and 21B in the xe2x80x9carrayxe2x80x9d and xe2x80x9ckerfxe2x80x9d areas respectively as illustrated in FIG. 2E. The thickness of STI oxide regions 21B is equal to about 150 nm. STI oxide regions 21A and 21B that result from that step, referred to hereinbelow as the STI fill/planarization step, will be subsequently used for device isolation and alignment mark definition respectively.
To that end, a second masking step is required. A layer 22 of photoresist is deposited on the wafer surface, then baked, exposed, and developed as standard to leave a patterned layer, that will be referred to hereinbelow as the KV mask still bearing numeral 22 as shown in FIG. 2F. The role of the KV mask 22 is to expose STI oxide regions 21B in the xe2x80x9ckerfxe2x80x9d areas to create the alignment marks.
After the KV mask 22 has been formed, the process continues with a wet etch step, that totally removes the STI oxide in STI oxide regions 21B defining thereby recesses in the silicon substrate 11 (with regards to the Si3N4 pad layer surface) located in the xe2x80x9ckerfxe2x80x9d areas that are referenced 23B in FIG. 2G.
Next, the residual photoresist material of layer 22 is removed from the wafer surface using a conventional strip process as illustrated in FIG. 2H.
Finally, the Si3N4 pad layer 12 is removed, leaving recesses 23B at desired locations of the silicon substrate 11 surface that will be used as alignment marks in the subsequent photolithography steps. The final structure 10 is shown in FIG. 2I. Alignment marks are essential in the fabrication process because they permit the correct registration of the mask reticles.
The above conventional method described by reference to FIGS. 2A-2I which requires two masking steps and which creates only recesses to be used as alignment marks is not satisfactory from a manufacturing point of view. The additional KV mask which is thus specifically required to create the alignment marks after STI oxide regions have been formed, must be designed for each semiconductor product. The KV masking step negatively affects both the cycle-time and tool capacity. Moreover, it consumes expensive photoresist materials and necessitates the fabrication of a specific reticle increasing thereby the overall manufacturing costs.
It is therefore a primary object of the present invention to provide a method of forming the STI oxide regions and alignment marks in a semiconductor structure provided with deep trenches with only one masking step.
It is another object of the present invention to provide a method of forming the STI oxide regions and alignment marks in a semiconductor structure provided with deep trenches in DRAM/EDRAM chips which avoids the masking step usually referred to as the KV mask.
It is another object of the present invention to provide a method of forming the STI oxide regions and alignment marks in a semiconductor structure provided with deep trenches in DRAM/EDRAM chips which not only allows the formation of recesses but also of bumps whenever desired to be subsequently used as alignment marks.
It is still another object of the present invention to provide a method of forming the STI oxide regions and alignment marks in a semiconductor structure provided with deep trenches in DRAM/EDRAM chips which improves process cycle-time and tool capacity to reduce the overall manufacturing costs.
The accomplishment of these objects and other related objects is achieved by the improved method of the present invention which applies to any semiconductor structure provided with polysilicon filled deep trenches formed in a silicon substrate coated by a Si3N4 pad layer both in the xe2x80x9carrayxe2x80x9d and xe2x80x9ckerfxe2x80x9d areas. First, a photoresist mask is formed onto the structure and patterned to expose the deep trenches only in the xe2x80x9carrayxe2x80x9d areas. Deep trenches are then anisotropically dry etched to create recesses having a determined depth. Next, the photoresist mask is removed only in the xe2x80x9carrayxe2x80x9d areas. A step of anisotropic dry etching is now performed to extend said recesses down to the desired depth to create the shallow isolation trenches. The photoresist mask is totally removed. A layer of oxide (STI oxide) is conformally deposited by LPCVD onto the structure to fill said shallow isolation trenches in excess. The structure is planarized to create the STI oxide regions and expose deep trenches in the xe2x80x9ckerfxe2x80x9d areas. The polysilicon in these deep trenches is partially or totally removed by etching. Finally, the Si3N4 pad layer is eliminated, creating recesses that will be used as alignment marks for the subsequent photolithography steps. If the polysilicon is not etched, the above method will produce polysilicon bumps instead that can be used for the same purpose.
The method of the present invention thus allows the simultaneous formation of the STI oxide regions and the alignment marks. An important aspect of the method of the present invention is to leave polysilicon (POLY3) in the deep trenches to create recesses to be subsequently used as alignment marks in the xe2x80x9ckerfxe2x80x9d areas, preventing them from being filled by the STI oxide and then to create recesses without using any mask by etching selectively to the STI oxide. This process also allows the formation of polysilicon (POLY3) bumps if so desired to be subsequently used as alignment marks.
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as these and other objects and advantages thereof, will be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.